The processing of semiconductor workpieces can involve deposition, patterning and removal of different materials layers on a substrate to form a multilayer structure. For better patterning alignment in 3D device structure fabrication, each layer is approximately planar. In each layer, dielectric materials such as silicate glasses can be used to separate structures and insulate conductive materials. Doped silicate glass including borosilicate glass (BSG), phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG) is commonly used as the dielectric or insulating layer between conductive materials because its melting point is typically much lower than regular glass or other dielectric materials. A lower melting temperature allows a reflow of doped silicate glass at a relative low temperature into patterned structures before planarization.
Silicate glass films can be deposited by plasma enhanced chemical vapor deposition (PECVD) system using liquid tetraethoxysilane (TEOS) as a source of silicon instead of hazardous silane gas. BSG, PSG or BPSG films can be deposited with addition of boron and phosphorus precursors in PECVD processes, respectively. The boron and/or phosphorus precursors could be organic or inorganic in nature. For instance, the boron precursors can include B2H6 and TEB (triethylborate), and the phosphorus precursors can include PH3 and TEPO (triethylphosphate).
Certain process manufacturing flow designs call for removal of reflowed doped silicate glass inside patterned structures, including some silicate glass liftoff processes in high capacity Dynamic Random Access Memory (DRAM) device fabrication. It is desirable to remove doped silicate glass with high selectivity towards other materials, such as undoped silicate glass, silicon nitride, titanium nitride, and silicon (e.g., polysilicon). Device dimension continues to decrease, and device structure aspect ratio continues to increase in semiconductor manufacturing. Thus the requirements on etch selectivity are becoming more stringent.
Wet etch processes are common in semiconductor manufacturing. However, conventional wet etch processes have some intrinsic problems and start to reach limitations in advanced semiconductor fabrications, especially in removing significant amount of materials inside small and high-aspect ratio structures. Wet etch rate can be limited by process temperature. It can be further constrained by a slow diffusion of wet etch chemical precursors into and wet etch chemical reaction products out of high aspect ratio nanostructures. In addition, a complete removal of wet chemicals from high aspect ratio nanostructures after the wet etch process can be very challenging, as most of the wet etch chemical precursors and wet etch reaction products are not volatile, thus prone to leave residues inside high aspect ratio nanostructures with standard wafer rinse and spin-dry processes. An insufficient post wet-etch wafer clean/dry can also result in surface corrosion and particle contamination on wafer surfaces. Finally, narrow and high aspect ratio nanostructures in advanced semiconductor devices are very fragile, and surface tension in wet etch processes can lead to significant pattern damage and sometimes pattern collapse and device failure.
Comparing with wet etch processes, vacuum based dry etch processes can be more effective, more efficient, more versatile and more suitable for materials removal inside high aspect ratio nanostructures. Workpiece temperature can be more flexible in dry etch processes to optimize etch rate and selectivity and to accommodate process integration requirements. In addition, vacuum based dry etch processes have better extendibility for materials removal inside high aspect ratio nanostructures with gas phase precursor adsorption and volatile reaction product desorption. Finally, as mentioned above, wet etch processes can have issues with surface tension induced pattern collapse and post etch residues inside high aspect ratio structures. They are in general not issues for gas phase based dry etch processes.